This invention relates to a high-speed serial interface, especially in a programmable logic device (PLD), which may operate at different data rates.
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial input/output (I/O) standards. Many of these standards can operate at more than one clock rate. Moreover, for any given clock rate, the clock rate may equal the data rate (this is referred to as “full rate” operation, in which data is clocked only on upward transitions of the clock signal), or the clock rate may be half the data rate (this is referred to as “half rate” operation, in which data is clocked on both upward and downward transitions of the clock signal, so that the clock rate is half of the effective data rate). However, it is a common feature of most if not all high-speed serial data protocols that neither the clock nor information about the clock is sent with the data. Instead, the clock must be recovered from the data.
For this purpose, it is known to use “clock data recovery” techniques in high-speed serial interfaces. Such techniques recover the clock from serial data using a closed-loop feedback system including, e.g., a phase-locked loop or delay-locked loop.
After the clock has been recovered, it is necessary to determine the data rate, which may, for example, be equal to the clock rate (“half rate” mode) or twice the clock rate (“full rate” mode), although other combinations of rates are possible. Frequently, that determination is made by logic in the PLD that is specific to the particular protocol, whether in the programmable logic of the PLD or in interface circuitry. For example, copending, commonly-assigned U.S. patent application Ser. No. 11/490,406, filed Jul. 19, 2006, describes an automatic rate negotiation mechanism that relies, for some rate changes, on a signal from the PLD logic indicating that a rate change is necessary. Such systems require the provision in the device of logic (hard logic or user-programmed logic), which may be dependent on the protocol in use (e.g., Gigabit Ethernet, Serial ATA, 1G, 2G, 4G or 8G Fibre Channel, Serial RapidIO, PCI-Express or PCI-Express 2.0, Infiniband, SerialLite, etc.), to assist in the rate negotiation.
It would be desirable to be able to provide, in a PLD transceiver, rate negotiation that is independent of the protocol in use and can operate independently of the remainder of the PLD.